When power is turned on to a computer system, an operating system (OS) startup process called a boot process (also called a “power-on reset sequence”) is initiated. The startup process includes initializing and diagnosing various pieces of hardware by OS and firmware such as BIOS (Basic input Output System), and configuring the various pieces of hardware into the computer system.
Further, during memory initialization, a memory recognizing process is performed in which the BIOS that is executed by a CPU (Central Processing Unit) instructs a memory controller to perform a read operation thereby reading memory module specification information (hereinafter called the “SPD (Serial Presence Detect) data”) stored in a nonvolatile memory (hereinafter called the “SPD memory”) mounted on a memory module.
Based on the SPD data which defines memory type and capacity, presence or absence of error checking, type of error checking, access timing, etc., the BIOS initializes RAM (Random Access Memory) mounted on the memory module and determines the method for controlling the memory module.
Usually, the SPD memory and the memory controller are connected by a serial bus whose transfer speed is slow. One example of such a serial bus is an I2C bus. The reason for using a slow serial bus is that the memory recognizing process is not frequently performed and, besides, the amount of the SPD data is small, so that a simple and low-cost bus is the logical choice. However, the slow transfer speed of the serial bus involves the problem that the memory initialization process becomes slow.
To enhance the speed of the memory recognizing process, there is proposed a technique in which the SPD data initially read by the CPU via a serial bus is stored in a memory accessible via a system bus so that the SPD data can be accessed more quickly when reading it for the second and subsequent times. Known examples of such a memory recognizing process include one disclosed in Japanese Unexamined Patent Publication No. 2007-122627.